Chip Scale Package Solder Joint Reliability Modeling and Material Characterization.
نویسندگان
چکیده
منابع مشابه
Wafer Level Chip Scale Pacakaging - Solder Joint Reliability
This paper will discuss the solder joint reliability aspects of a new wafer level Chip Scale Package (CSP) form factor. The CSP requires no leadframe or interposer tooling. It is the same size as the die, and was originally developed for low-pin count analog devices for pitches from 0.8 mm down to 0.5 mm. The package has been demonstrated with eutectic solder bumps on 8-lead devices. The form f...
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ژورنال
عنوان ژورنال: Journal of Japan Institute of Electronics Packaging
سال: 2000
ISSN: 1343-9677,1884-121X
DOI: 10.5104/jiep.3.45